Today I am leaving the University of York to take up a new job at Rapita Systems.
I would like to thank the staff of the
Real-time Systems Research Group
(RTSRG) for their support during my time there, including the years I spent
working on my PhD thesis (2004-2008) and the years I spent working on FP7
I don't want to write an list of people that I would like to thank, since
I am sure to forget important details. But I would like to thank
Dr Neil Audsley
for his supervision and advice on too many matters to reliably enumerate.
Neil built up the impressive collection of FPGA-based systems in
the RTS lab, and it is thanks to his support that I was able to pick up the skills
needed to use them effectively with VHDL/Verilog and (more recently) Bluespec
System Verilog (BSV). Neil reviewed countless drafts of papers and I have
often wondered if any of them would have been accepted without his revisions
and rewrites. Neil is an extremely experienced academic supervisor and anyone
can do well with his advice.