Collection of Scratchpad Memory FPGA designs
Thursday, 2 August 2012
Here is a list of FPGA designs incorporating scratchpad memory (SPM) and related technologies, created by myself during the last few years for research and teaching purposes.The number of these designs has proliferated recently, due to the need to support various different research papers and projects. I thought it would be useful to categorise the FPGA designs and explain how they differ from each other. All of these have been published online and can surely be used for research and teaching purposes - however, note that the University of York retains copyright on the code, so you need to get permission if you want to use them in some commercial design.
- Explicitly-reservable cache (ercache)
Purpose: Cache support for multitasking real-time operating system with exactly-known cache-related preemption delay. Single task, data only.
Public URL: http://rtslab.wikispaces.com/file/view/tecs-july-2012.tar.bz2
Internal SVN: /rtslab/carousel/tecs/fpga_hardware (revision 483)
Type: XPS IP core (version 13.4)
Data Interfaces: Data Local Memory Bus (DLMB), Xilinx NPI
Control Interface: FSL
Associated paper: Submitted to ACM TECS
Description: A direct-mapped data cache with support for explicitly saving and restoring state upon context switch.
Online publish date: 3rd July 2012
FPGA target: ML505
Status: Test cases are working, but Carousel OS integration is incomplete.
- Data SPM with DMA unit (dmaspm)Purpose:
To support a student project about SPM-optimised sorting algorithms, and
to provide raw data for
the presentation at ECRTS 2012. Single task, data only.
Public URL: http://rtslab.wikispaces.com/file/view/spmsort-package-1.tar.xz
Internal SVN: /rtslab/studentprojects/2012/jack.01/hardware and /rtslab/carousel/dmaspm(revision 483)
Type: XPS IP core (version 13.4)
Data Interfaces: Data Local Memory Bus (DLMB), Xilinx NPI
Control Interface: FSL
Associated paper: Student project https://rtslab.wikispaces.com/Project+jack.01+2012
Description: A data SPM linked to a DMA unit and a Microblaze CPU
Online publish date: 23rd July 2012
FPGA target: ML505
Status: Working. Tested using example sort programs included in the package. ECRTS presentation material in SVN includes some integration with ELA-1 algorithm and csearch.
- Carousel version 3.03
Purpose: Scratchpad support for multitasking real-time operating system. Multiple tasks, instructions and data.
Public URL: http://www-users.cs.york.ac.uk/~jack/carousel_v3_03_a.tar.bz2
Internal SVN: /rtslab/carousel/srpd/fpgahw (revision 483)
Type: XPS IP core (version 13.4)
Data Interfaces: Instruction Local Memory Bus (ILMB), Data Local Memory Bus (DLMB), Xilinx Cache Link
Control Interface: FSL
Associated paper: None
Description: Hardware implementation of multitasking scratchpad reuse scheme (MSRS) for data and instructions. Carries out save and restore operations upon context switch. The SPM is divided into a read-only and a read-write area.
FPGA target: ML505
Status: Working. Tested with Carousel OS example and with measure.py.
- Carousel version 2.0Purpose:
Scratchpad support for multitasking real-time operating system. Multiple
tasks, instructions only.
Public URL: http://rtslab.wikispaces.com/file/view/msrs-dist-3.tar.bz2
Internal SVN: /rtslab/carousel/rtss12 (revision 505)
Type: XPS IP core (version 10.1)
Data Interfaces: Instruction Local Memory Bus (ILMB), Xilinx Cache Link
Control Interface: FSL
Associated paper: Accepted by IEEE RTSS 2012
Description: Hardware implementation of multitasking scratchpad reuse scheme (MSRS) for instructions only. Carries out save and restore operations upon context switch
Online publish date: 13th August 2012
FPGA target: ML505
Status: Working. Tested with Carousel OS example and with measure.py.
- Scratchpad Memory Management Unit (smmu)
Purpose: Loading and using dynamically-allocated data structures with an SPM. Single task, data only.
Public URL: http://jwhitham.org/c/smmu/smmu_kit_1.03.tar.bz2
Type: XPS IP core (version 10.1)
Data Interface: Data Local Memory Bus (DLMB), Processor Local Bus (PLB)
Control Interface: Memory-mapped registers
Associated paper: Several, see http://jwhitham.org/c/smmu.html
Description: Hardware implementation of an SPM with dynamic address translation (SMMU) such that objects can be mapped to SPM without changing their logical address.
Online publish date: March 2010
FPGA target: ML505
Status: Working.
Notes: Carousel version 1.0 was only implemented in a simulator (paper at RTAS 2012).